Device for calculating FSM bits in the UMTS standard

ABSTRACT

The invention relates to a device for calculating FSM bits by means of which the signals sent from two antennas of a base station are influenced with reference to their phase difference and/or their amplitudes. The FSM bits are calculated with the aid of two estimated channel impulse responses. The device is present in hard-wired form.

RELATED APPLICATION

This application is a national stage application of InternationalApplication No. PCT/DE03/01036 filed Mar. 28, 2003, which is entitled“DEVICE FOR CALCULATING FSM BITS IN THE UMTS STANDARD”, which was notpublished in English, and claims priority to German Patent ApplicationSerial No. 102 17 853.4, which was filed on Apr. 22, 2002, which ishereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

The invention relates to a device with the aid of which it is possibleto calculate the FSM bits that determine the antenna weightings of abase station; particularly in the UMTS standard.

BACKGROUND OF THE INVENTION

In the case of a mobile radio system that comprises a base station withtwo antennas and a mobile radio subscriber, a fixed phase relationshipis set up between the two transmission channels, which are to beassigned in each case to one of the antennas of the base station. In theUMTS (Universal Mobile Telecommunications System) standard, a so-calledCLTD (Closed Loop Mode Transmit Diversity) function can be used toinfluence the relationship of the signals emitted by two antennas inorder thereby to achieve constructive interference of the twotransmission channels. The CLTD function can be operated in a mode 1 anda mode 2. The phase of one of the two antennas can be varied in mode 1.The phase of the other antenna remains fixed. The overall result is tovary the phase relationship between the two antennas. In addition to thevariation, known from mode 1, in the phase relationship, mode 2 providesa variation in the amplitudes of the signals emitted from the antennas.The amplitudes of both antennas can be varied in mode 2.

The CLTD function is described in the 3GPP TS 25.214 UMTS specification.This specification is referenced repeatedly below. All data refer inthis case to the V4.2.0 (2001-09) version.

FSM (Feedback Signalling Message) data words that are transmitted to thebase station are formed in the mobile radio terminal from estimatedchannel impulse responses by means of the CLTD function. The channelimpulse responses of both channels are always used in this case for anFSM data word. The FSM data words include information specific to thebase station and relating to the optimum phase relationship and, ifappropriate, relating to the optimum amplitudes of the signals to beemitted from the two antennas.

Two antenna weightings w₁ and w₂ that are applied to the signals whichare to be emitted from the two antennas are formed in the base stationfrom an FSM data word. The antenna weightings w₁ and w₂ are complex andhave the following form:w ₁=α₁ +jβ ₁  (1)w ₂=α₂ +jβ ₂  (2)

Two diversity components are evaluated by multiplying the signals to beemitted by the antenna weightings w₁ and w₂. In this case, the antennaweightings w₁ and w₂ are selected with the aim of maximizing per slotthe energy received by the mobile radio terminal while taking account ofthe weight quantization prescribed in the UMTS standard. This isequivalent to maximizing a proportionality factor P that is given by thefollowing equation:

$\begin{matrix}{P = {{{{\overset{\rightarrow}{w}}^{H}\begin{bmatrix}H_{11} & H_{12} \\H_{21} & H_{22}\end{bmatrix}}\overset{\rightarrow}{w}} = {{{\overset{\rightarrow}{w}}^{H}\left( {\sum\limits_{m = 1}^{M}{H_{m}^{H}H_{m}}} \right)}\overset{\rightarrow}{w}}}} & (3)\end{matrix}$

Here, the index m denotes the respective base station m (m=1, . . . ,M). Furthermore, it holds for the matrix H_(m) and the vector w that:H_(m)=[{right arrow over (h)}_(m,1),{right arrow over (h)}_(m,2)]  (4){right arrow over (w)}=[w₁,w₂]^(T)  (5)

The indices 1 and 2 relate to two antennas i of a base station m. {rightarrow over (h)}_(m,i) are complex (N_(m)×1) vectors that stand for thechannel impulse responses estimated by the channel estimator with achannel depth N_(m). Each vector {right arrow over (h)}_(m,i) is to beassociated with one of the antennas i of the base station m. It is to beassumed without loss of generality for the following considerations thatonly one base station m is sending (M=1). The index m is thereforeomitted below, thus simplifying equation (4):H=[{right arrow over (h)}₁,{right arrow over (h)}₂]  (6)With i, j=1, 2, it holds for the elements H_(ij) of the matrix fromequation (3) that:

$\begin{matrix}{{H_{i\; j} = {{{\overset{\rightarrow}{h}}_{i}^{H}{\overset{\rightarrow}{h}}_{j}} = {{H_{i\; j}}{\mathbb{e}}^{{j\varphi}_{H_{i\; j}}}}}},} & (7)\end{matrix}$

|H_(ij)| specifying a modulus and φ_(H) _(ij) phase angle.

Consequently, the technical problem to be solved includes adetermination of the antenna weightings w₁ and w₂ per slot in such a waythat the proportionality factor P is maximized for given estimatedchannel impulse responses {right arrow over (h)}_(i)=[h_(i,1), . . . ,h_(i,n), . . . , h_(i,N)]^(T). The boundary conditions for the valueranges of the antenna weightings w₁ and w₂ are to be observed in thisprocess.

The following boundary conditions hold for the antenna weightings w₁ andw₂ in mode 1 of the CLTD function:

$\begin{matrix}{w_{1} = \frac{1}{\sqrt{2}}} & (8) \\{w_{2} = {\frac{1}{\sqrt{2}}{\mathbb{e}}^{j\;\varphi_{2}}}} & (9) \\{\varphi_{2} \in \left\{ {0,\frac{\pi}{2},\pi,{- \frac{\pi}{2}}} \right\}} & (10)\end{matrix}$

In this case, the phase angle φ₂(s) is a function of the slot index s(s=1, 2, . . . , S). More detailed explanations of this are to be foundin section 7.2 of the 3GPP TS 25.214 V4.2.0 UMTS specification.

The following boundary conditions hold for the antenna weightings w₁ andw₂ in mode 2 of the CLTD function:

$\begin{matrix}{w_{1} = \sqrt{E_{1}}} & (11) \\{w_{2} = {\sqrt{E_{2}}{\mathbb{e}}^{j\;\varphi_{2}}}} & (12) \\{E_{1},{E_{2} \in \left\{ {0.2,0.8} \right\}}} & (13) \\{{E_{1} + E_{2}} = 1} & (14) \\{\varphi_{2} \in \left\{ {0,\frac{\pi}{4},\frac{\pi}{2},\frac{3\pi}{4},\pi,{- \frac{\pi}{4}},{- \frac{\pi}{2}},{- \frac{3\pi}{4}}} \right\}} & (15)\end{matrix}$

Here, the amplitudes E₁(s) and E₂(s) as well as the phase angle φ₂(s)are functions of the slot index s (s=1, 2, . . . , S). Mode 2 isdescribed in more detail in section 7.3 of the 3GPP TS 25.214 V4.2.0UMTS specification.

To date, the optimum values for the phase angle φ₂(s) and, ifappropriate, for the amplitudes E₁(s) and E₂(s) have been determined asa function of the mode and slot index s by parameterizing equation (3)or by substituting the values in question. In this process, it isnecessary in mode 1 to make a selection from only two phase angle valuesper slot. By contrast, it is necessary in mode 2 to evaluate 16combinations of amplitude and phase angle. This problem has been solvedto date by means of a digital signal processor because of the structureof the calculating algorithm. In this process, the digital signalprocessor generates on the output side an FSM data word which consistsof FSM bits and includes information relating to the optimum values forthe phase angle φ₂(s) and, if appropriate, for the amplitudes E₁(s) andE₂(s).

SUMMARY OF THE INVENTION

It is an object of the invention to create a device with the aid ofwhich FSM bits can be determined as a function of the mode and slotindex in a particularly efficient fashion. A corresponding method forcalculating the FSM bits is also to be specified.

The device according to the invention serves for calculating FSM bits bymeans of which the signals sent from two antennas of a base station areinfluenced with reference to their phase difference and/or theiramplitudes. The FSM bits are calculated with the aid of two estimatedchannel impulse responses. In this process, a channel impulse responseis related in each case to the channel belonging to one of the antennas.An essential idea of the invention resides in the fact that the deviceis hard-wired. It is therefore present as a hardware circuit.

Owing to the hardware design of the device according to the invention,the latter can carry out the required calculations substantially moreefficiently than a digital signal processor. Furthermore, the deviceaccording to the invention is more favorable in terms of outlay than adigital signal processor.

The device forms a complex phasor from components of the two channelimpulse responses and then generates an FSM bit by means of rotation andprojection of the phasor and, in particular, of a threshold valuedecision. In particular, the channel coefficients, which are combined ina channel impulse response for each channel, can be complex. It is thenalso possible for the real or imaginary part of a channel coefficient toform a component of a channel impulse response.

The device advantageously has inputs, control inputs and an output.Components of the two channel impulse responses are applied to theinputs, and control signals are applied to the control inputs. Thispermits the device to calculate the FSM bit as a function of thecomponents of the two channel impulse responses and the control signals.The FSM bit can be tapped at the output of the device.

A preferred refinement of the invention provides that the deviceincludes a logic unit and a processing unit that is connected downstreamof the logic unit.

The logic unit preferably has an equal number of inputs and outputs. Thecomponents of the two channel impulse responses are present at theinputs of the logic unit. The inputs of the logic unit are connected tothe outputs of the logic unit as a function of at least one controlsignal.

In accordance with a further preferred refinement of the invention, amultiplier stage, an adder, a weighting stage, an accumulator and athreshold value decision unit are arranged in series in the processingunit.

It can preferably be provided in this case that the multiplier stageincludes two multipliers that in each case multiply by one another twovalues supplied by the logic unit. For this purpose, the inputs of themultipliers are connected in each case to two outputs of the logic unit.The multiplication results for the two multipliers are added by theadder.

The sum formed by the adder is advantageously multiplied by a weightingfactor in the weighting stage. The weighting factor results from acontrol signal that is present at the weighting stage.

A particularly preferred refinement of the invention is characterized inthat the control signals are stored in the form of control bits in aread-only memory. This measure permits a calculating speed of the FSMbits that is higher by comparison with a digital signal processor.

The device according to the invention is, furthermore, designed withparticular preference for the UMTS standard.

In the case of a device operating according to the UMTS standard, thecontrol signals are preferably a function both of the slot number of theFSM bit whose calculation is pending at this instant, and of the CLTDmode. Owing to this refinement, the device is designed with sufficientflexibility to be able to carry out different types of calculations forall combinations of slot number and CLTD mode.

In accordance with a preferred refinement of the invention, the valuesof the control signals are a function of whether the slot number is aneven or odd number.

The device according to the invention can be implemented with particularadvantage in the associated mobile radio terminal.

FSM bits are calculated by means of the method according to theinvention using two estimated channel impulse responses. In a firstmethod step, a complex phasor is produced from components of the twochannel impulse responses. In a second method step, this phasor is usedto calculate an FSM bit by means of rotation, projection and, inparticular, a threshold value decision. The method according to theinvention is distinguished by a particularly efficient and quickcalculation of the FSM bit.

BRIEF DESCRIPTIONS OF THE DRAWINGS

The invention is explained below in more detail by way of example withreference to the drawings, in which:

FIG. 1 shows a schematic block diagram of an exemplary embodiment of thedevice according to the invention;

FIG. 2 shows a diagram of the mode of operation of the device accordingto the invention in the plane of complex numbers for mode 1; and

FIG. 3 shows a diagram of the mode of operation of the device accordingto the invention in the plane of complex numbers for mode 2.

DETAILED DESCRIPTION OF THE INVENTION

A circuit 1 is illustrated in FIG. 1 as an exemplary embodiment for thedevice according to the invention. The circuit 1 comprises logic units 2and 3, multipliers 4 and 5, an adder 6, a weighting unit 7, anaccumulator 8 and a threshold value decision unit 9.

The logic unit 2 has inputs In1, In2, In3 and In4, configuration inputsConfig1 and Config2 and outputs Out1, Out2, Out3 and Out4. The inputsIn1, In2, In3 and In4 of the logic unit 2 are simultaneously inputs ofthe circuit 1. The logic unit 3 has inputs In5 and In6, configurationinputs Config3, Config4 and Config5 and outputs Out5 and Out6. Themultipliers 4 and 5 and the adder 6 each have two inputs and one output.The weighting unit 7, the accumulator 8 and the threshold value decisionunit 9 respectively comprise an input and an output. Furthermore, theweighting unit 7 includes a configuration input Config6. The output ofthe threshold value decision unit 9 constitutes the output of thecircuit 1.

The output Out3 of the logic unit 2 is connected to the input In5 of thelogic unit 3. The output Out4 of the logic unit 2 is connected to theinput In6 of the logic unit 3.

One input of the multiplier 4 is coupled to the output Out1 of the logicunit 2. The second input of the multiplier 4 is coupled to the outputOut5 of the logic unit 3.

One input of the multiplier 5 is coupled to the output Out2 of the logicunit 2. The second input of the multiplier 5 is coupled to the outputOut6 of the logic unit 3.

The outputs of the multipliers 4 and 5 feed the inputs of the adder 6.Connected downstream of the adder 6 are the weighting unit 7, theaccumulator 8 and the threshold value decision unit 9 in the prescribedsequence.

The circuit 1 is integrated in this case in a mobile radio terminaloperating in accordance with the UMTS standard, and serves forgenerating FSM bits. The FSM bits are subsequently transmitted to theassociated base station in which antenna weightings are produced fromthe FSM bits.

The base station has two antennas. Consequently, complex channelcoefficients h_(i,n) with a channel depth N are calculated by a channelestimator for two channels i (i=1, 2; n=1, 2, . . . , N). The channelcoefficients h_(i,n) are combined for each channel i to form anN-component vector as channel impulse response {right arrow over(h)}_(i)=[h_(i,1), . . . , h_(i,n), . . . , h_(i,N)]^(T). During theduration of a slot s, the real and imaginary parts of the channelcoefficients h_(1,n) and h_(2,n) are present at the inputs In1, In2, In3and In4 of the circuit 1. The configuration bits C_(1,k)(s), C_(2,k)(s),. . . , C_(6,k)(s) are present at the configuration inputs Config 1,Config 2, . . . , Config 6. In accordance with the 3GPP TS 25.214 V4.2.0UMTS specification, the slot index s runs from 1 to 15. The clock indexk-runs through the integral values from 1 to 2N. The path index n andthe clock index k are in the ratio 1:2. This means that a channelcoefficient h_(i,n) is present two system clocks for processing on thecircuit 1.

The mode of operation of the circuit 1 is as follows. The logic units 2and 3 connect their inputs In1, . . . , In6 to their outputs Out1, . . ., Out6 as a function of the configuration bits C_(1,k)(s), . . . ,C_(5,k)(s). This produces a complex number a_(k)+jb_(k) at the outputsOut1 and Out2, a complex number c_(k)+jd_(k) at the outputs Out3 andOut4, and a complex number e_(k)+jf_(k) at the outputs Out5 and Out6. Onthe output side, the multipliers 4 and 5 produce real numbers A_(k) andB_(k), respectively, the adder 6 produces a real number S_(k), and theweighting unit 7 produces a real number R_(k) as a function of theconfiguration bit C_(6,k)(s). The accumulator 8 accumulates over twicethe channel depth 2N, and produces a variable X(s) on the output side.The threshold value decision unit 9 uses the variable X(s) to generatean FSM bit FSM(s) with the aid of the following distinction betweencases:X(s)<0

FSM(s)=0  (16)X(s)≧0

FSM(s)=1  (16)

The following Table 1 gives the precise mode of operation of the circuit1:

C_(1,k)(s), No. a_(k) + jb_(k) c_(k) + jd_(k) C_(2,k)(s) 1. k even:Re{h_(1,n)(s)} + k even: Re{h_(2,n)(s)} + 1, 1 jIm{h_(1,n)(s)}jIm{h_(2,n)(s)} k odd: 0 k odd: 0 X 2. k even: Re{h_(1,n)(s)} + k even:Re{h_(2,n)(s)} + 1, 1 jIm{h_(1,n)(s)} jIm{h_(2,n)(s)} k odd: 0 k odd: 0X 3. Re{h_(1,n)(s)} + Re{h_(2,n)(s)} + 1, 1 jIm{h_(1,n)(s)}jIm{h_(2,n)(s)} 4. Re{h_(1,n)(s)} + Re{h_(2,n)(s)} + 1, 1jIm{h_(1,n)(s)} jIm{h_(2,n)(s)} 5. Re{h_(1,n)(s)} + Re{h_(2,n)(s)} + 1,1 jIm{h_(1,n)(s)} jIm{h_(2,n)(s)} 6. Re{h_(1,n)(s)} + Re{h_(2,n)(s)} +1, 1 jIm{h_(1,n)(s)} jIm{h_(2,n)(s)} 7. Re{h_(1,n)(s)} +Re{h_(2,n)(s)} + 1, 1 jIm{h_(1,n)(s)} jIm{h_(2,n)(s)} 8.Re{h_(1,n)(s)} + Re{h_(2,n)(s)} + 1, 1 jIm{h_(1,n)(s)} jIm{h_(2,n)(s)}9. k even: Re{h_(1,n)(s)} + k even: Re{h_(1,n)(s)} + 1, 0jIm{h_(1,n)(s)} jIm{h_(1,n)(s)} k odd: Re{h_(2,n)(s)} + k odd:Re{h_(2,n)(s)} + 0, 1 jIm{h_(2,n)(s)} jIm{h_(2,n)(s)} No. e_(k) + jf_(k)C_(3,k)(s), C_(4,k)(s), C_(5,k)(s) A_(k) B_(k) S_(k) 1. k even: c_(k) +jd_(k) 1, 1, 1 a_(k)e_(k) b_(k)f_(k) A_(k) + B_(k) k odd: 0 X 2. k even:−d_(k) + jc_(k) 0, 0, 1 a_(k)e_(k) b_(k)f_(k) A_(k) + B_(k) k odd: 0 X3. k even: c_(k) + jd_(k) 1, 1, 1 a_(k)e_(k) b_(k)f_(k) A_(k) + B_(k) kodd: −d_(k) + jc_(k) 0, 0, 1 4. k even: c_(k) + jd_(k) 1, 1, 1a_(k)e_(k) b_(k)f_(k) A_(k) + B_(k) k odd: d_(k) − jc_(k) 1, 1, 0 5. keven: −c_(k) − jd_(k) 1, 0, 0 a_(k)e_(k) b_(k)f_(k) A_(k) + B_(k) k odd:−d_(k) + jc_(k) 0, 0, 1 6. k even: c_(k) + jd_(k) 1, 1, 1 a_(k)e_(k)b_(k)f_(k) A_(k) + B_(k) k odd: −d_(k) + jc_(k) 0, 0, 1 7. k even:c_(k) + jd_(k) 1, 1, 1 a_(k)e_(k) b_(k)f_(k) A_(k) + B_(k) k odd: d_(k)− jc_(k) 0, 1, 0 8. k even: −c_(k) − jd_(k) 1, 0, 0 a_(k)e_(k)b_(k)f_(k) A_(k) + B_(k) k odd: d_(k) − jc_(k) 0, 1, 0 9. k even:c_(k) + jd_(k) 1, 1, 1 a_(k)e_(k) b_(k)f_(k) A_(k) + B_(k) k odd: −c_(k)− jd_(k) 1, 0, 0 No. R_(k) C_(6,k)(s) X (s) 1. k even: 1 · S_(k) 1Re{H₂₁(s)} k odd: 0 X 2. k even: 1 · S_(k) 1 Im{H₂₁(s)} k odd: 0 X 3. keven: tan(π/8) · S_(k) 0 Im{H₂₁(s) · exp(jπ/8)/cos(π/8)} k odd: 1 ·S_(k) 1 4. k even: 1 · S_(k) 1 Re{H₂₁(s) · exp(jπ/8)/cos(π/8)} k odd:tan(π/8) · S_(k) 0 5. k even: tan(π/8) · S_(k) 0 Im{H₂₁(s) ·exp(−jπ/8)/cos(π/8)} k odd:: 1 · S_(k) 1 6. k even: 1 · S_(k) 1Re{H₂₁(s) · exp(−jπ/8)/cos(π/8)} k odd: tan(π/8) · S_(k) 0 7. k even:tan(π/8) · S_(k) 0 −Im{H₂₁(s) · exp(−jπ/8)/cos(π/8)} k odd:: 1 · S_(k) 18. k even: 1 · S_(k) 1 −Re{H₂₁(s) · exp(−jπ/8)/cos(π/8)} k odd: tan(π/8)· S_(k) 0 9. k even: 1 · S_(k) 1 |H₁₁(s)|² − |H₂₂(s)|² k odd: 1 · S_(k)1

The three blocks of Table 1 set forth one below the other are to beunderstood such that each row of a block is continued in thecorresponding row of the subsequent block.

The stipulations which produce the configuration bits C_(1,k)(s),C_(2,k)(s), . . . , C_(6,k)(s) can be read off from Table 1.

For C_(1,k)(s)=1 and C_(2,k)(s)=1, the inputs In1, . . . , In4 of thelogic unit 2 are connected to the outputs Out1, . . . , Out4respectively situated opposite them in FIG. 1. For C_(1,k)(s)=0, theinputs In1 and In2 are applied to the outputs Out3 and Out4,respectively. For C_(2,k)(s)=0, the inputs In3 and In4 are applied tothe outputs Out1 and Out2, respectively.

The configuration bit C_(3,k)(s) decides on the assignment of theoutputs Out5 and Out6 of the logic unit 3 to the inputs In5 and In6. ForC_(3,k)(s)=1, the input In5 is applied to the output Out5, and the inputIn6 is applied to the output Out6. For C_(3,k)(s)=0, the input In5 isapplied to the output Out6, and the input In6 is applied to the outputOut5.

The configuration bits C_(4,k)(s) and C_(5,k)(s) determine the signs ofthe outputs Out5 and Out6, respectively. For C_(4,k)(s)=1 andC_(5,k)(s)=1, the outputs Out5 and Out6 have a positive sign, while forC_(4,k)(s)=0 and C_(5,k)(s)=0 the signs of the outputs Out5 and Out6 arenegative.

The configuration bit C_(6,k)(s) decides on the weighting that isapplied to the number S_(k) in the weighting unit 7. For C_(6,k)(s)=1,the number S_(k) remains unchanged, while for C_(6,k)(s)=0 the numberS_(k) is multiplied by the factor tan(π/8).

A value “X” in Table 1 for one of the conguration bits C_(1,k)(s), . . ., C_(6,k)(s) means that the block is not clocked and therefore does notproduce a new output.

In order to be able to apply Table 1, a need further exists to stipulatethe row of Table 1 that is to be considered. Such a row specification isprovided by Table 2, which is set forth below and forms a relationshipbetween the combination of CLTD mode and slot index s with the rownumbers of Table 1.

CLTD mode/slot combination No. from Table 1 Mode 1 1 s even Mode 2 2 sodd Mode 2 3 s modulo 4 = 0 Mode 2 4 s modulo 4 = 1 Mode 2 5 or 6 or 7or 8 s modulo 4 = 2 Mode 2 9 s modulo 4 = 3

Given s modulo 4=2, in mode 2 a selection is made between the rownumbers 5, 6, 7 or 8 of Table 1 as a function of the results of FSM(s−1)and FSM(s−2). The corresponding assignments can be read off at theentries of Table 3, which is set forth below.

FSM (s − 2) FSM (s − 1) No. from Table 1 0 0 7 0 1 8 1 0 6 1 1 5

Note that in accordance with 3GPP TS 25.214 V4.2.0 UMTS specification,in mode 1 one FSM data word consists of an FSM bit FSM(s), and in mode 2it consists of four FSM bits FSM(s). Consequently, in mode 1 withprogressive slot index s Nos. 1 and 2 from Table 1 are used alternatelyfor configuring circuit 1. In mode 2, rows Nos. 3, 4, 5 to 8 and 9 areselected on the basis of the four FSM bits FSM(s) of the FSM data wordwith a periodicity of 4 with reference to the slot index s.

The entries in Tables 1 and 2 are preferably stored in a read-onlymemory and therefore need not be calculated during processing.

The relationships on which the entries in Tables 1 and 2 are based areexplained below.

For all CLTD mode/slot combinations, the calculation of an FSM bitFSM(s) can be reduced to merely considering one or two elements Hij ofthe matrix from equation (3). The elements Hij are subjected to the sameprocessing in order to calculate an FSM bit FSM(s). This processingconsists essentially of rotations and projections.

The matrix element H₂₁=|H₂₁|e^(jφ) ^(H) ₂₁ is considered for CLTDmode/slot combinations in which the FSM bit FSM(s) pronounces on thephase angle φ₂. The derivation of equation (3) in terms of the phaseangle φ₂ leads to the maximum value of the proportionality factor P forboth CLTD modes and for φ₂=φ_(H) ₂₁ .

The matrix elements H₁₁ and H₂₂ are considered for CLTD mode/slotcombinations in which the FSM bit FSM(s) pronounces on the moduli of theantenna weightings w₁ and w₂. Taking account of the stipulations of the3GPP TS 25.214 V4.2.0 UMTS specification, in accordance with which theamplitudes E₁(s) and E₂(s) can assume only two values, this requiresonly that the difference |H₁₁|²−|H₂₂|² be evaluated.

The specific processing operations for different CLTD mode/slotcombinations differ from one another, in particular, in the rotation ofthe complex phasor, given by the matrix element H₂₁, in the plane ofcomplex numbers, and in its projection onto the real or imaginary axis.The respective processing operation is controlled by means of theconfiguration bits C_(1,k)(s), . . . , C_(6,k)(s). The 9 possibleprocessing cases of circuit 1 are listed in Table 1.

The constellations in the plane of complex numbers that have to beevaluated in mode 1 are illustrated in FIG. 2.

Section 7.2 of the 3GPP TS 25.214 V4.2.0 UMTS specification stipulatesthat during normal operation of the CLTD function in mode 1, that is tosay outwith an initialization or a so-called compressed mode, it isnecessary to evaluate for an even slot index s whether the complexphasor H₂₁ in FIG. 2 lies in the bright complex half plane, that is tosay in the 1^(st) or 4^(th) quadrant, or in the dark complex half plane,that is to say in the 2^(nd) or 3^(rd) quadrant. It is necessary toevaluate for an odd slot index s whether the complex phasor H₂₁ lies inthe stippled complex half plane, that is to say in the 1^(st) or 2^(nd)quadrant, or in the dashed complex half plane, that is to say in the3^(rd) or 4^(th) quadrant. Given the progressive slot index s, bothtasks are accomplished by the alternate use of rows Nos. 1 and 2 fromTable 1.

The constellations in the plane of complex numbers that have to beevaluated in mode 2 are illustrated in FIG. 3.

Here, as well, the circuit 1 is to be described in the normal operatingmode of the CLTD function in mode 2, that is to say outwith a so-calledend of frame adjustment, an initialization or a compressed mode. It isdescribed below how the four FSM bits FSM(s) of the FSM data word areobtained for a phasor H₂₁ with |H₁₁|>|H₂₂| in the plane of complexnumbers in the angular segment between π/8 and 3π/8. This phasor H₂₁ isdepicted in FIG. 3.

Row No. 3 from Table 1 is to be applied for s=0 in mode 2 according toTable 2. In accordance with row No. 3 from Table 1, it is necessary toinvestigate whether the term Im{H₂₁(s)·e^(jπ/8)/cos(π/8)} specifying thevariable X(s) is positive or negative. This term clearly specifies thatthe phasor H₂₁ is rotated counterclockwise by the angle π/8 in the planeof complex numbers because of the multiplication by the factor e^(jπ/8),is stretched by the factor 1/cos(π/8), and is subsequently projectedonto the imaginary axis. An investigation is thereupon conducted as towhether this projection lies on the positive or the negative halfstraight line of the imaginary axis. In the plane of complex numbers,the operations described can be replaced by a threshold value decision.It is necessary for this purpose to investigate whether the phasor H₂₁lies above or below the straight line A depicted in FIG. 3. The straightline A is rotated clockwise by the angle π/8 in relation to the realaxis, and thereby compensates the counterclockwise rotation of thephasor H₂₁ by the angle π/8. In the present case, the phasor H₂₁ liesabove the straight line A, and so the FSM bit FSM(0) assumes the value1.

The rotation by the angle π/8 or −π/8 is taken into account in thecircuit 1 by using the weightings 1 and tan(π/8) in the weighting unit7. In this case, the phasor H₂₁ is stretched by the factor 1/cos(π/8),but this is not significant for the statement relating to the angle.

For s=1, row No. 4 from Table 1 is used in mode 2 according to Table 2for the purpose of calculating the FSM bit FSM(1). It is thereforenecessary here to consider the term Re{H₂₁(s)·e^(jπ/8)/cos(π/8)}. In acorresponding way to the procedure in the case of s=0, it is necessaryin this case to investigate on which side of the straight line Bdepicted in FIG. 3 the phasor H₂₁ lies. The straight line B results froma clockwise rotation of the real axis by an angle of π/8. A value of 1results in this case for the FSM bit FSM(1).

According to row No. 5 from Table 1, for s=2 an evaluation must takeplace with reference to the straight line C depicted in FIG. 3. Thestraight line C is rotated clockwise by the angle π/8 with reference tothe imaginary axis. A value of 1 results for the FSM bit FSM(2).

Row No. 9 from Table 1 is used for s=3. This leads to a value of 1 forthe FSM bit FSM(3). In total, the FSM data word resulting from thephasor H₂₁ is 1111.

Various possible positions of the phasor H₂₁ are marked by crosses byway of example in FIG. 3. The FSM data words associated with thesepositions are noted next to them.

List of reference symbols 1 Circuit 2 Logic unit 3 Logic unit 4Multiplier 5 Multiplier 6 Adder 7 Weighting unit 8 Accumulator 9Threshold value decision unit In1, . . . , In6 Inputs Config1, . . . ,Config6 Configuration inputs Out1, . . . , Out6 Outputs h_(i,n)(s)Channel coefficients Re{h_(1,n)(s)}, Real parts of channelRe{h_(2,n)(s)} coefficients Im{h_(1,n)(s)}, Imaginary parts of channelIm{h_(2,n)(s)} coefficients FSM (s) FSM bit C_(1,k)(s), C_(2,k)(s), . .. , C_(6,k)(s) Configuration bits i Channel (i = 1, 2) s Slot index (s =1, . . . , 15) n Path index (n = 1, . . . , N) k Clock index (k = 1, . .. , 2N) a_(k), c_(k), e_(k) Real parts b_(k), d_(k), f_(k) Imaginaryparts a_(k) + jb_(k), c_(k) + jd_(k), e_(k) + jf_(k) Complex numbersA_(k), B_(k), S_(k), R_(k) Numbers X (s) Variable H₂₁ Complex phasor A,B, C Straight lines

1. A device for calculating feedback signaling message (FSM) bits, comprising: a circuit configured to calculate feedback signaling message (FSM) bits by means of which the signals sent from two antennas of a base station are influenced with reference to their phase difference and/or their amplitudes with the aid of the two estimated channel impulse responses, wherein the circuit is in hard-wired form, wherein the circuit is configured to generate a first complex phasor from first components of the two channel impulse responses and a second complex phasor from second components of the two channel impulse responses, and further configured to produce a first FSM bit by a rotation and projection of the first phasor and a comparison of the rotated and projected first phasor with a constant threshold value and configured to produce a second FSM bit by a rotation and projection of the second phasor and a comparison of the rotated and projected second phasor with the constant threshold value, and wherein the first and the second components of the two channel impulse responses comprise different components.
 2. The device as claimed in claim 1, wherein the components of the two channel impulse responses are applied at inputs of the circuit, and wherein control signals are applied at control inputs of the circuit, and wherein the FSM bit is provided at an output of the circuit, the FSM bit being calculated as a function of the components of the two channel impulse responses and the control signals.
 3. The device as claimed in claim 2, wherein the circuit comprises a logic unit configure to receive and selectively arrange the two channel impulse responses, and a processing unit connected downstream of the logic unit configured to process the two channel impulse responses based on the selective arrangement thereof.
 4. The device as claimed in claim 3, wherein the components of the two channel impulse responses are present at inputs of the logic unit, wherein the logic unit has outputs whose number is equal to the number of its inputs, and wherein the inputs of the logic unit are connected to the outputs of the logic unit as a function of at least one of the control signals.
 5. The device as claimed in claim 3, wherein the processing unit comprises a multiplier stage, an adder, a weighting stage, an accumulator and a threshold value decision unit connected in series in the prescribed sequence.
 6. The device as claimed in claim 5, wherein the multiplier stage has two multipliers, whose inputs are connected in each case to two outputs of the logic unit, and wherein the inputs of the adder are connected to the outputs of the multipliers.
 7. The device as claimed in claim 6, further comprising a control signal coupled as an input to the weighting stage, and wherein the weighting stage applies is configured to apply a weighting factor to a sum formed by the adder as a function of the control signal coupled thereto.
 8. The device as claimed in claim 2, wherein the control signals are stored in the form of control bits in a read-only memory.
 9. The device as claimed in claim 1, wherein the circuit is designed for the UMTS standard.
 10. The device as claimed in claim 9, wherein the control signals are a function of the slot number of the FSM bit to be calculated, and of a CLTD mode.
 11. The device as claimed in claim 10, wherein the control signals are a function of whether the slot number of the FSM bit to be calculated is an even or odd number.
 12. A mobile radio terminal having a device as claimed in claim
 1. 13. A method for calculating FSM bits utilizing a device which determines antenna weightings of a base station, comprising: producing a first complex phasor from first components of two estimated channel impulse responses and a second complex phasor from second components of the two estimated channel impulse responses; and calculating a first FSM bit by rotation and projection of the first phasor and a second FSM bit by rotation and projection of the second phasor, wherein the first and second FSM bits influence signals sent from two antennas of a base station with reference to their phase difference and/or their amplitudes with the aid of the two estimated channel impulse responses, and wherein the first and the second components of the two channel impulse responses comprise different components.
 14. The method as claimed in claim 13, wherein the rotation and projection of the phasor is determined by control signals.
 15. The method as claimed in claim 13, wherein calculating the FSM bit comprises performing a threshold value comparison after the rotation and projection of the phasor.
 16. The method as claimed in claim 14, wherein the method is designed for the UMTS standard.
 17. The method as claimed in claim 16, wherein the control signals are a function of the slot number of the FSM bit to be calculated, and of a CLTD mode.
 18. The method as claimed in claim 17, wherein the control signals are a function of whether the slot number of the FSM bit to be calculated is an even or odd number. 